Programmers are increasingly turning to managed languages, such as Java and C#, because they decrease development time and the resulting programs have fewer defects. However, many architects and systems researchers do not yet evaluate or design new approaches for these workloads, retarding innovation. One reason may be that measuring managed languages has a number of challenges, such as how to factor in and out dynamic compilation and garbage collection. This talk shows the pitfalls of ignoring these effects, and recommends methodologies for measuring managed languages in a meaningful way.

Kathryn McKinley is a professor at The University of Texas at Austin. She received her PhD, MS, and BA from Rice University. Her research interests include compiler optimization, architecture, memory management, and software engineering. She has published over 75 refereed articles. Her honors include ACM Distinguished Scientist and she currently serves as the co-Editor-in-Chief of TOPLAS. She has graduated eight PhD students and is currently supervising eight graduate students.

Continued growth in compute power coupled with the growth in massive online data has enabled more pervasive use of effective modeling and simulation of events, objects, and concepts in real-time. We find such processing needs at the heart of many emerging applications and services. This processing can be decomposed three fundamental computing capabilities: recognition, mining, and synthesis (RMS). A set of RMS workloads is examined in terms of usage, mathematical models, numerical algorithms, and underlying data structures. Our analysis suggests a workload convergence that has implications in computing platforms. A diverse set of RMS applications is emerging from market segments such as graphics, gaming, media-mining, unstructured information management, financial analyses, and interactive virtual communities. These applications present a relatively focused and highly overlapping set of common platform challenges and an opportunity for an effective representation of these emerging workloads in future benchmark and performance suites.

Pradeep Dubey is a senior principal engineer and manager of Innovative Platform Architecture (IPA) in the Microprocessor Technology Lab, part of the Corporate Technology Group at Intel. His research focus is computer architectures to efficiently handle new application paradigms for the future computing environment. Dubey previously worked at IBM's T.J. Watson Research Center, and Broadcom Corporation. He was one of the principal architects of the AltiVec* multimedia extension to Power PC* architecture. He also worked on the design, architecture, and performance issues of various microprocessors, including Intel's i386TM, i486TM, and Pentium processors. He holds over 25 patents and has published extensively. Dr. Dubey received a BS in electronics and communication engineering from Birla Institute of Technology, India, an MSEE from the University of Massachusetts at Amherst, and a PhD in electrical engineering from Purdue University. He is a Fellow of IEEE.

The Department of Defense High Performance Computing Modernization Program (HPCMP) has carefully prepared a comprehensive application benchmarking suite based on the workload of its user community. It has updated that application benchmarking suite annually over the past eight years to determine the performance of offered systems during the program's yearly acquisition of HPC capability. As part of that process, each HPC system in the program's current inventory is benchmarked with that year's suite, and an overall capability is determined for each system based on a weighted average over all test cases in the suite. The performance of the overall set of HPCMP systems is tracked over time as a program performance metric. The evolution of the application benchmarking suite and the historical track of HPCMP system performance using these benchmarked-based metrics will be discussed.

Larry P. Davis has more than 30 years experience in science and technology. He is one of the founders and currently the Deputy Director of the DoD High Performance Computing Modernization Program (HPCMP) in the Institute for Defense Analyses. Dr. Davis also is responsible for HPCMP's benchmarking and performance modeling activities. Davis has published over twenty refereed journal articles in addition to numerous technical reports.