SPEC(R) CINT2006 Summary Hewlett Packard Enterprise ProLiant DL385 Gen10 (2.10 GHz, AMD EPYC 7251) Test Sponsor: HPE Mon Jan 1 06:25:15 2001 CPU2006 License: 3 Test date: Dec-2017 Test sponsor: HPE Hardware availability: Nov-2017 Tested by: HPE Software availability: Sep-2017 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 32 606 516 S 400.perlbench 32 606 516 S 400.perlbench 32 606 516 * 401.bzip2 32 806 383 S 401.bzip2 32 803 384 * 401.bzip2 32 797 388 S 403.gcc 32 481 536 * 403.gcc 32 480 537 S 403.gcc 32 481 536 S 429.mcf 32 377 774 S 429.mcf 32 374 780 S 429.mcf 32 375 778 * 445.gobmk 32 666 504 * 445.gobmk 32 664 506 S 445.gobmk 32 682 492 S 456.hmmer 32 278 1070 * 456.hmmer 32 277 1080 S 456.hmmer 32 286 1040 S 458.sjeng 32 859 451 * 458.sjeng 32 863 449 S 458.sjeng 32 859 451 S 462.libquantum 32 106 6230 S 462.libquantum 32 107 6230 S 462.libquantum 32 106 6230 * 464.h264ref 32 1028 689 * 464.h264ref 32 1029 688 S 464.h264ref 32 1028 689 S 471.omnetpp 32 458 437 S 471.omnetpp 32 458 437 * 471.omnetpp 32 461 433 S 473.astar 32 529 425 S 473.astar 32 531 423 S 473.astar 32 529 425 * 483.xalancbmk 32 305 723 S 483.xalancbmk 32 306 721 * 483.xalancbmk 32 308 718 S ============================================================================== 400.perlbench 32 606 516 * 401.bzip2 32 803 384 * 403.gcc 32 481 536 * 429.mcf 32 375 778 * 445.gobmk 32 666 504 * 456.hmmer 32 278 1070 * 458.sjeng 32 859 451 * 462.libquantum 32 106 6230 * 464.h264ref 32 1028 689 * 471.omnetpp 32 458 437 * 473.astar 32 529 425 * 483.xalancbmk 32 306 721 * SPECint(R)_rate_base2006 690 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: AMD EPYC 7251 CPU Characteristics: AMD Turbo CORE technology up to 2.90 GHz CPU MHz: 2100 FPU: Integrated CPU(s) enabled: 16 cores, 2 chips, 8 cores/chip, 2 threads/core CPU(s) orderable: 1, 2 chip(s) Primary Cache: 64 KB I + 32 KB D on chip per core Secondary Cache: 512 KB I+D on chip per core L3 Cache: 32 MB I+D on chip per chip Other Cache: None Memory: 1 TB (16 x 64 GB 4Rx4 PC4-2666V-L, running at 2400) Disk Subsystem: 1 x 400 GB SAS SSD, RAID 0 Other Hardware: None SOFTWARE -------- Operating System: SUSE Linux Enterprise Server 12 (x86_64) SP3 Kernel 4.4.73-5-default Compiler: C/C++: Version 4.5.2.1 of x86 Open64 Compiler Suite (from AMD) Auto Parallel: No File System: xfs System State: Run level 3 (multi-user) Base Pointers: 32/64-bit Peak Pointers: Not Applicable Other Software: MicroQuill SmartHeap 10.0 32-bit Library for Linux Submit Notes ------------ The config file option 'submit' was used. 'numactl' was used to bind copies to the cores. See the configuration file for details. Operating System Notes ---------------------- Set vm/nr_hugepages=86016 in /etc/sysctl.conf mount -t hugetlbfs nodev /mnt/hugepages Platform Notes -------------- BIOS Configuration: Thermal Configuration set to Maximum Cooling Performance Determinism set to Power Deterministic Memory Patrol Scrubbing set to Disabled Workload Profile set to General Throughput Compute Minimum Processor Idle Power Core C-State set to C6 State Processor Power and Utilization Monitoring set to Disabled General Notes ------------- Environment variables set by runspec before the start of the run: HUGETLB_LIMIT = "896" LD_LIBRARY_PATH = "/home/cpu2006/amd1603-rate-libs-revB/32:/home/cpu2006/amd1603-rate-libs-revB/64" The binaries were built with the x86 Open64 Compiler Suite, which is only available from (and supported by) AMD at http://developer.amd.com/tools-and-sdks/cpu-development/x86-open64-compiler-suite/ Base Compiler Invocation ------------------------ C benchmarks: opencc C++ benchmarks: openCC Base Portability Flags ---------------------- 400.perlbench: -DSPEC_CPU_LP64 -DSPEC_CPU_LINUX_X64 401.bzip2: -DSPEC_CPU_LP64 403.gcc: -DSPEC_CPU_LP64 429.mcf: -DSPEC_CPU_LP64 445.gobmk: -DSPEC_CPU_LP64 456.hmmer: -DSPEC_CPU_LP64 458.sjeng: -DSPEC_CPU_LP64 462.libquantum: -DSPEC_CPU_LP64 -DSPEC_CPU_LINUX 464.h264ref: -DSPEC_CPU_LP64 483.xalancbmk: -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -Ofast -CG:local_sched_alg=1 -INLINE:aggressive=ON -IPA:plimit=8000 -IPA:small_pu=100 -HP:bd=2m:heap=2m -mso -LNO:prefetch=2 -march=bdver1 -mno-fma4 -mno-xop -mno-tbm C++ benchmarks: -Ofast -m32 -INLINE:aggressive=on -CG:cmp_peep=on -D__OPEN64_FAST_SET -march=bdver1 -mno-fma4 -mno-xop -mno-tbm -L/root/work/libraries/SmartHeap-10/lib -lsmartheap The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2006/flags/x86-openflags-rate-revA-I.html http://www.spec.org/cpu2006/flags/HPE-Platform-Flags-AMD-V1.2-EPYC-revD.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2006/flags/x86-openflags-rate-revA-I.xml http://www.spec.org/cpu2006/flags/HPE-Platform-Flags-AMD-V1.2-EPYC-revD.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2018 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.2. Report generated on Tue Mar 6 12:09:19 2018 by CPU2006 ASCII formatter v6932. Originally published on 14 January 2018.