SPEC(R) CINT2006 Summary IBM Corporation IBM System x3950 Sat Dec 16 01:05:44 2006 CPU2006 License: 11 Test date: Dec-2006 Test sponsor: IBM Corporation Hardware availability: Oct-2006 Tested by: IBM Corporation Software availability: Aug-2006 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 16 1886 82.9 S 400.perlbench 16 1884 83.0 * 400.perlbench 16 1884 83.0 S 401.bzip2 16 3157 48.9 S 401.bzip2 16 3166 48.8 S 401.bzip2 16 3160 48.9 * 403.gcc 16 6413 20.1 S 403.gcc 16 6456 19.9 * 403.gcc 16 6547 19.7 S 429.mcf 16 3293 44.3 S 429.mcf 16 3300 44.2 S 429.mcf 16 3298 44.2 * 445.gobmk 16 2230 75.3 S 445.gobmk 16 2224 75.5 S 445.gobmk 16 2224 75.5 * 456.hmmer 16 2630 56.8 * 456.hmmer 16 2625 56.9 S 456.hmmer 16 2636 56.6 S 458.sjeng 16 3238 59.8 S 458.sjeng 16 3353 57.7 S 458.sjeng 16 3272 59.2 * 462.libquantum 16 13535 24.5 S 462.libquantum 16 13556 24.5 * 462.libquantum 16 13558 24.5 S 464.h264ref 16 2532 140 S 464.h264ref 16 2536 140 * 464.h264ref 16 2537 140 S 471.omnetpp 16 3647 27.4 * 471.omnetpp 16 3647 27.4 S 471.omnetpp 16 3652 27.4 S 473.astar 16 2172 51.7 S 473.astar 16 2175 51.6 S 473.astar 16 2174 51.7 * 483.xalancbmk 16 1641 67.3 S 483.xalancbmk 16 1640 67.3 * 483.xalancbmk 16 1635 67.5 S ============================================================================== 400.perlbench 16 1884 83.0 * 401.bzip2 16 3160 48.9 * 403.gcc 16 6456 19.9 * 429.mcf 16 3298 44.2 * 445.gobmk 16 2224 75.5 * 456.hmmer 16 2630 56.8 * 458.sjeng 16 3272 59.2 * 462.libquantum 16 13556 24.5 * 464.h264ref 16 2536 140 * 471.omnetpp 16 3647 27.4 * 473.astar 16 2174 51.7 * 483.xalancbmk 16 1640 67.3 * SPECint(R)_rate_base2006 50.8 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon 7120N CPU Characteristics: 667 MHz bus CPU MHz: 3000 FPU: Integrated CPU(s) enabled: 8 cores, 4 chips, 2 cores/chip, 2 threads/core CPU(s) orderable: 1,2,4 chips Primary Cache: 12 K micro-ops I + 16 KB D on chip per core Secondary Cache: 1 MB I+D on chip per core L3 Cache: 4 MB I+D on chip per chip Other Cache: None Memory: 32 GB (16 x 2048 MB ECC PC2-3200) Disk Subsystem: 73 GB SAS, 10k RPM Other Hardware: None SOFTWARE -------- Operating System: Microsoft Windows Server 2003 Enterprise x64 Edition + SP1 (64-bit) Compiler: Intel C++ Compiler for IA32 version 9.1 Build no 20060816 Microsoft Visual Studio .Net 2003 (for libraries) Auto Parallel: No File System: NTFS System State: Default Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: Smart Heap Library, Version 8 General Notes ------------- Bios Settings Hardware Prefetch enabled Memory Array set to High-Performance Memory Array Base Compiler Invocation ------------------------ C benchmarks: icl -Qvc7.1 -Qc99 C++ benchmarks: icl -Qvc7.1 Base Portability Flags ---------------------- 403.gcc: -DSPEC_CPU_WIN32 464.h264ref: -DSPEC_CPU_NO_INTTYPES -DWIN32 Base Optimization Flags ----------------------- C benchmarks: -fast /F512000000 shlw32m.lib -link /FORCE:MULTIPLE C++ benchmarks: -fast -Qcxx_features /F512000000 shlw32m.lib -link /FORCE:MULTIPLE Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags file that was used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.01.html You can also download the XML flags source by saving the following link: http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.01.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2014 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.0. Report generated on Tue Jul 22 10:13:00 2014 by CPU2006 ASCII formatter v6932. Originally published on 25 January 2007.