SPEC(R) CINT2006 Summary IBM Corporation IBM System x3800 Mon Dec 11 04:55:40 2006 CPU2006 License: 11 Test date: Dec-2006 Test sponsor: IBM Corporation Hardware availability: Oct-2006 Tested by: IBM Corporation Software availability: Aug-2006 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 16 1655 94.5 S 400.perlbench 16 1655 94.4 S 400.perlbench 16 1655 94.5 * 401.bzip2 16 1764 87.5 S 401.bzip2 16 1762 87.6 S 401.bzip2 16 1763 87.6 * 403.gcc 16 5387 23.9 * 403.gcc 16 5372 24.0 S 403.gcc 16 5427 23.7 S 429.mcf 16 2207 66.1 S 429.mcf 16 2208 66.1 * 429.mcf 16 2210 66.0 S 445.gobmk 16 1932 86.9 S 445.gobmk 16 1935 86.7 S 445.gobmk 16 1934 86.8 * 456.hmmer 16 2303 64.8 S 456.hmmer 16 2307 64.7 S 456.hmmer 16 2303 64.8 * 458.sjeng 16 2798 69.2 S 458.sjeng 16 2804 69.1 * 458.sjeng 16 2829 68.4 S 462.libquantum 16 13296 24.9 S 462.libquantum 16 13307 24.9 S 462.libquantum 16 13304 24.9 * 464.h264ref 16 2150 165 S 464.h264ref 16 2152 165 * 464.h264ref 16 2153 164 S 471.omnetpp 16 2717 36.8 S 471.omnetpp 16 2712 36.9 S 471.omnetpp 16 2715 36.8 * 473.astar 16 1458 77.0 S 473.astar 16 1463 76.7 * 473.astar 16 1468 76.5 S 483.xalancbmk 16 1180 93.5 S 483.xalancbmk 16 1178 93.7 * 483.xalancbmk 16 1177 93.8 S ============================================================================== 400.perlbench 16 1655 94.5 * 401.bzip2 16 1763 87.6 * 403.gcc 16 5387 23.9 * 429.mcf 16 2208 66.1 * 445.gobmk 16 1934 86.8 * 456.hmmer 16 2303 64.8 * 458.sjeng 16 2804 69.1 * 462.libquantum 16 13304 24.9 * 464.h264ref 16 2152 165 * 471.omnetpp 16 2715 36.8 * 473.astar 16 1463 76.7 * 483.xalancbmk 16 1178 93.7 * SPECint(R)_rate_base2006 64.8 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon 7140N CPU Characteristics: 667 MHz bus CPU MHz: 3333 FPU: Integrated CPU(s) enabled: 8 cores, 4 chips, 2 cores/chip, 2 threads/core CPU(s) orderable: 1,2,4 chips Primary Cache: 12 K micro-ops I + 16 KB D on chip per core Secondary Cache: 1 MB I+D on chip per core L3 Cache: 16 MB I+D on chip per chip Other Cache: None Memory: 32 GB (16 x 2048 MB ECC PC2-3200) Disk Subsystem: 73 GB SAS, 10k RPM Other Hardware: None SOFTWARE -------- Operating System: Microsoft Windows Server 2003 Enterprise x64 Edition + SP1 (64-bit) Compiler: Intel C++ Compiler for IA32 version 9.1 Build no 20060816 Microsoft Visual Studio .Net 2003 (for libraries) Auto Parallel: No File System: NTFS System State: Default Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: Smart Heap Library, Version 8 General Notes ------------- Bios Settings Hardware Prefetch enabled Memory Array set to High-Performance Memory Array Base Compiler Invocation ------------------------ C benchmarks: icl -Qvc7.1 -Qc99 C++ benchmarks: icl -Qvc7.1 Base Portability Flags ---------------------- 403.gcc: -DSPEC_CPU_WIN32 464.h264ref: -DSPEC_CPU_NO_INTTYPES -DWIN32 Base Optimization Flags ----------------------- C benchmarks: -fast /F512000000 shlw32m.lib -link /FORCE:MULTIPLE C++ benchmarks: -fast -Qcxx_features /F512000000 shlw32m.lib -link /FORCE:MULTIPLE Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags file that was used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.01.html You can also download the XML flags source by saving the following link: http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.01.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2014 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.0. Report generated on Tue Jul 22 10:12:48 2014 by CPU2006 ASCII formatter v6932. Originally published on 25 January 2007.