SPEC® CINT2006 Result

Copyright 2006-2014 Standard Performance Evaluation Corporation

Itautec

Servidor Itautec ZX440, Intel Xeon 7110M processor

SPECint®_rate2006 = Not Run

CPU2006 license: 9001 Test date: Dec-2006
Test sponsor: Itautec Hardware Availability: Jul-2006
Tested by: Itautec Software Availability: May-2006
Benchmark results graph
Hardware
CPU Name: Intel Xeon 7110M
CPU Characteristics: Dual Core, 2.60 GHz, 800MHz System Bus
CPU MHz: 2600
FPU: Integrated
CPU(s) enabled: 8 cores, 4 chips, 2 cores/chip, 2 threads/core
CPU(s) orderable: 1-4 chips
Primary Cache: 12 K micro-ops I + 16 KB D on chip per core
Secondary Cache: 1 MB I+D on chip per core
L3 Cache: 4 MB I+D on chip per chip
Other Cache: None
Memory: 16 GB (16x1GB DDR2-RAM, PC2-3200R, CAS 3-3-3)
Disk Subsystem: 36 GB SCSI, 10000RPM
Other Hardware: None
Software
Operating System: Windows Server 2003 Enterprise Edition + SP1
(32-bit)
Compiler: Intel C++ Compiler for IA32 version 9.1
Package ID W_CC_C_9.1.025 Build no 20060519Z
Auto Parallel: No
File System: NTFS
System State: Default
Base Pointers: 32-bit
Peak Pointers: Not Applicable
Other Software: Microquill SmartHeap Library v.8.0 for SMP

Results Table

Benchmark Base Peak
Copies Seconds Ratio Seconds Ratio Seconds Ratio Copies Seconds Ratio Seconds Ratio Seconds Ratio
Results appear in the order in which they were run. Bold underlined text indicates a median measurement.
400.perlbench 16 2247 69.6 2367 66.0 2377 65.8
401.bzip2 16 3530 43.7 3517 43.9 3523 43.8
403.gcc 16 5643 22.8 5714 22.5 5695 22.6
429.mcf 16 2824 51.7 2822 51.7 2824 51.7
445.gobmk 16 2559 65.6 2545 66.0 2555 65.7
456.hmmer 16 3049 49.0 3048 49.0 3048 49.0
458.sjeng 16 3795 51.0 3758 51.5 3782 51.2
462.libquantum 16 11053 30.0 11047 30.0 11062 30.0
464.h264ref 16 2954 120   2953 120   2955 120  
471.omnetpp 16 3132 31.9 3131 31.9 3131 31.9
473.astar 16 2338 48.0 2339 48.0 2341 48.0
483.xalancbmk 16 1940 56.9 1936 57.0 1936 57.0

Platform Notes

Bios Settings:
  Hardware Prefetch enabled:
  prefetch data in order to shorten execution
  cycles and maximize data processing efficiency.

  Snoop Filter enabled:
  Preserves cache coherency while minimizing snoops to remote nodes.

  Memory Array set to High-Performance Memory Array:
  Memory is up to 4-way interleaved (Memory RAID disabled).

Base Compiler Invocation

C benchmarks:

 icl   -Qvc7.1   -Qc99 

C++ benchmarks:

 icl   -Qvc7.1 

Base Portability Flags

403.gcc:  -DSPEC_CPU_WIN32 
464.h264ref:  -DSPEC_CPU_NO_INTTYPES   -DWIN32 

Base Optimization Flags

C benchmarks:

 -fast   /F512000000   shlSMPMt.lib    -link /FORCE:MULTIPLE 

C++ benchmarks:

 -fast   -Qcxx_features   /F512000000   shlSMPMt.lib    -link /FORCE:MULTIPLE 

Base Other Flags

C benchmarks:

403.gcc:  -Dalloca=_alloca 

The flags file that was used to format this result can be browsed at
http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.html.

You can also download the XML flags source by saving the following link:
http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.xml.

SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders.

For questions about this result, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2006-2014 Standard Performance Evaluation Corporation
Tested with SPEC CPU2006 v1.0.
Report generated on Tue Jul 22 10:42:28 2014 by SPEC CPU2006 HTML formatter v6932.
Originally published on 10 January 2007.