SPEC(R) CPU2017 Integer Rate Result Cisco Systems Cisco UCS B480 M5 (Intel Xeon Gold 6134M 3.20 GHz) CPU2017 License: 9019 Test date: Nov-2018 Test sponsor: Cisco Systems Hardware availability: Aug-2017 Tested by: Cisco Systems Software availability: Mar-2018 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate --------------- ------- --------- --------- ------- --------- --------- 500.perlbench_r 64 619 165 * 64 506 202 * 500.perlbench_r 64 622 164 S 64 505 202 S 500.perlbench_r 64 613 166 S 64 506 202 S 502.gcc_r 64 488 186 S 64 407 223 * 502.gcc_r 64 487 186 * 64 407 223 S 502.gcc_r 64 486 186 S 64 408 222 S 505.mcf_r 64 395 262 S 64 394 263 * 505.mcf_r 64 391 265 S 64 394 262 S 505.mcf_r 64 392 264 * 64 383 270 S 520.omnetpp_r 64 657 128 S 64 659 127 S 520.omnetpp_r 64 657 128 * 64 658 128 S 520.omnetpp_r 64 650 129 S 64 659 127 * 523.xalancbmk_r 64 290 233 S 64 246 275 S 523.xalancbmk_r 64 291 233 * 64 246 275 * 523.xalancbmk_r 64 292 231 S 64 245 276 S 525.x264_r 64 258 435 S 64 245 458 * 525.x264_r 64 256 437 S 64 244 458 S 525.x264_r 64 257 436 * 64 246 456 S 531.deepsjeng_r 64 384 191 S 64 385 191 * 531.deepsjeng_r 64 384 191 * 64 384 191 S 531.deepsjeng_r 64 383 191 S 64 385 191 S 541.leela_r 64 603 176 * 64 587 181 S 541.leela_r 64 599 177 S 64 595 178 S 541.leela_r 64 606 175 S 64 592 179 * 548.exchange2_r 64 403 416 S 64 403 416 * 548.exchange2_r 64 403 416 * 64 404 415 S 548.exchange2_r 64 404 416 S 64 403 416 S 557.xz_r 64 452 153 S 64 451 153 S 557.xz_r 64 452 153 S 64 453 153 S 557.xz_r 64 452 153 * 64 451 153 * ================================================================================= 500.perlbench_r 64 619 165 * 64 506 202 * 502.gcc_r 64 487 186 * 64 407 223 * 505.mcf_r 64 392 264 * 64 394 263 * 520.omnetpp_r 64 657 128 * 64 659 127 * 523.xalancbmk_r 64 291 233 * 64 246 275 * 525.x264_r 64 257 436 * 64 245 458 * 531.deepsjeng_r 64 384 191 * 64 385 191 * 541.leela_r 64 603 176 * 64 592 179 * 548.exchange2_r 64 403 416 * 64 403 416 * 557.xz_r 64 452 153 * 64 451 153 * SPECrate2017_int_base 216 SPECrate2017_int_peak 230 HARDWARE -------- CPU Name: Intel Xeon Gold 6134M Max MHz.: 3700 Nominal: 3200 Enabled: 32 cores, 4 chips, 2 threads/core Orderable: 2,4 Chips Cache L1: 32 KB I + 32 KB D on chip per core L2: 1 MB I+D on chip per core L3: 24.75 MB I+D on chip per chip Other: None Memory: 1536 GB (48 x 32 GB 2Rx4 PC4-2666V-R) Storage: 1 x 400 GB SSD SAS Other: None SOFTWARE -------- OS: SUSE Linux Enterprise Server 12 SP2 (x86_64) 4.4.120-92.70-default Compiler: C/C++: Version 18.0.2.199 of Intel C/C++ Compiler for Linux; Fortran: Version 18.0.2.199 of Intel Fortran Compiler for Linux Parallel: No Firmware: Version 3.2.3c released Mar-2018 File System: xfs System State: Run level 3 (multi-user) Base Pointers: 64-bit Peak Pointers: 32/64-bit Other: jemalloc: jemalloc memory allocator library V5.0.1; Submit Notes ------------ The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" General Notes ------------- Environment variables set by runcpu before the start of the run: LD_LIBRARY_PATH = "/home/cpu2017/lib/ia32:/home/cpu2017/lib/intel64:/home/cpu2017/je5.0.1-32:/home/cpu2017/je5.0.1-64" Binaries compiled on a system with 1x Intel Core i7-4790 CPU + 32GB RAM memory using Redhat Enterprise Linux 7.4 Transparent Huge Pages enabled by default Prior to runcpu invocation Filesystem page cache synced and cleared with: sync; echo 3> /proc/sys/vm/drop_caches runcpu command invoked through numactl i.e.: numactl --interleave=all runcpu Yes: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2) is mitigated in the system as tested and documented. jemalloc: configured and built at default for 32bit (i686) and 64bit (x86_64) targets; jemalloc: built with the RedHat Enterprise 7.4, and the system compiler gcc 4.8.5; jemalloc: sources available from jemalloc.net or https://github.com/jemalloc/jemalloc/releases Platform Notes -------------- BIOS Settings: Intel HyperThreading Technology set to Enabled CPU performance set to Enterprise Power Performance Tuning set to OS Controls SNC set to Enabled IMC Interleaving set to 1-way Interleave Patrol Scrub set to Disabled Sysinfo program /home/cpu2017/bin/sysinfo Rev: r5797 of 2017-06-14 96c45e4568ad54c135fd618bcc091c0f running on linux-xy4f Fri Nov 9 06:21:22 2018 SUT (System Under Test) info as seen by some common utilities. For more information on this section, see https://www.spec.org/cpu2017/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Gold 6134M CPU @ 3.20GHz 4 "physical id"s (chips) 64 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 8 siblings : 16 physical 0: cores 0 2 3 9 16 19 26 27 physical 1: cores 0 2 3 9 16 19 26 27 physical 2: cores 0 2 3 9 16 19 26 27 physical 3: cores 0 2 3 9 16 19 26 27 From lscpu: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 64 On-line CPU(s) list: 0-63 Thread(s) per core: 2 Core(s) per socket: 8 Socket(s): 4 NUMA node(s): 8 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Gold 6134M CPU @ 3.20GHz Stepping: 4 CPU MHz: 1545.024 CPU max MHz: 3700.0000 CPU min MHz: 1200.0000 BogoMIPS: 6399.97 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 25344K NUMA node0 CPU(s): 0,1,3,4,32,33,35,36 NUMA node1 CPU(s): 2,5-7,34,37-39 NUMA node2 CPU(s): 8,9,11,12,40,41,43,44 NUMA node3 CPU(s): 10,13-15,42,45-47 NUMA node4 CPU(s): 16,17,19,20,48,49,51,52 NUMA node5 CPU(s): 18,21-23,50,53-55 NUMA node6 CPU(s): 24,25,27,28,56,57,59,60 NUMA node7 CPU(s): 26,29-31,58,61-63 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch ida arat epb invpcid_single pln pts dtherm hwp hwp_act_window hwp_epp hwp_pkg_req intel_pt rsb_ctxsw spec_ctrl stibp retpoline kaiser tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx avx512f avx512dq rdseed adx smap clflushopt clwb avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 cqm_llc cqm_occup_llc /proc/cpuinfo cache data cache size : 25344 KB From numactl --hardware WARNING: a numactl 'node' might or might not correspond to a physical chip. available: 8 nodes (0-7) node 0 cpus: 0 1 3 4 32 33 35 36 node 0 size: 192095 MB node 0 free: 190042 MB node 1 cpus: 2 5 6 7 34 37 38 39 node 1 size: 193528 MB node 1 free: 191716 MB node 2 cpus: 8 9 11 12 40 41 43 44 node 2 size: 193528 MB node 2 free: 191723 MB node 3 cpus: 10 13 14 15 42 45 46 47 node 3 size: 193528 MB node 3 free: 191706 MB node 4 cpus: 16 17 19 20 48 49 51 52 node 4 size: 193528 MB node 4 free: 191711 MB node 5 cpus: 18 21 22 23 50 53 54 55 node 5 size: 193528 MB node 5 free: 191723 MB node 6 cpus: 24 25 27 28 56 57 59 60 node 6 size: 193528 MB node 6 free: 191719 MB node 7 cpus: 26 29 30 31 58 61 62 63 node 7 size: 193525 MB node 7 free: 191708 MB node distances: node 0 1 2 3 4 5 6 7 0: 10 11 21 21 21 21 21 21 1: 11 10 21 21 21 21 21 21 2: 21 21 10 11 21 21 21 21 3: 21 21 11 10 21 21 21 21 4: 21 21 21 21 10 11 21 21 5: 21 21 21 21 11 10 21 21 6: 21 21 21 21 21 21 10 11 7: 21 21 21 21 21 21 11 10 From /proc/meminfo MemTotal: 1583915128 kB HugePages_Total: 0 Hugepagesize: 2048 kB From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 2 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12-SP2" VERSION_ID="12.2" PRETTY_NAME="SUSE Linux Enterprise Server 12 SP2" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12:sp2" uname -a: Linux linux-xy4f 4.4.120-92.70-default #1 SMP Wed Mar 14 15:59:43 UTC 2018 (52a83de) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Jan 1 21:36 SPEC is set to: /home/cpu2017 Filesystem Type Size Used Avail Use% Mounted on /dev/sda1 xfs 224G 82G 142G 37% / Additional information from dmidecode follows. WARNING: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Cisco Systems, Inc. B480M5.3.2.3c.0.0307181316 03/07/2018 Memory: 48x 0xCE00 M393A4K40BB2-CTD 32 GB 2 rank 2666 (End of data from sysinfo program) Compiler Version Notes ---------------------- ============================================================================== CC 500.perlbench_r(base) 502.gcc_r(base) 505.mcf_r(base, peak) 525.x264_r(base, peak) 557.xz_r(base, peak) ------------------------------------------------------------------------------ icc (ICC) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== CC 500.perlbench_r(peak) 502.gcc_r(peak) ------------------------------------------------------------------------------ icc (ICC) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== CXXC 520.omnetpp_r(base) 523.xalancbmk_r(base) 531.deepsjeng_r(base) 541.leela_r(base) ------------------------------------------------------------------------------ icpc (ICC) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== CXXC 520.omnetpp_r(peak) 523.xalancbmk_r(peak) 531.deepsjeng_r(peak) 541.leela_r(peak) ------------------------------------------------------------------------------ icpc (ICC) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== FC 548.exchange2_r(base, peak) ------------------------------------------------------------------------------ ifort (IFORT) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ Base Compiler Invocation ------------------------ C benchmarks: icc -m64 -std=c11 C++ benchmarks: icpc -m64 Fortran benchmarks: ifort -m64 Base Portability Flags ---------------------- 500.perlbench_r: -DSPEC_LP64 -DSPEC_LINUX_X64 502.gcc_r: -DSPEC_LP64 505.mcf_r: -DSPEC_LP64 520.omnetpp_r: -DSPEC_LP64 523.xalancbmk_r: -DSPEC_LP64 -DSPEC_LINUX 525.x264_r: -DSPEC_LP64 531.deepsjeng_r: -DSPEC_LP64 541.leela_r: -DSPEC_LP64 548.exchange2_r: -DSPEC_LP64 557.xz_r: -DSPEC_LP64 Base Optimization Flags ----------------------- C benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/home/cpu2017/je5.0.1-64/ -ljemalloc C++ benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/home/cpu2017/je5.0.1-64/ -ljemalloc Fortran benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -nostandard-realloc-lhs -align array32byte -L/home/cpu2017/je5.0.1-64/ -ljemalloc Peak Compiler Invocation ------------------------ C benchmarks (except as noted below): icc -m64 -std=c11 502.gcc_r: icc -m32 -std=c11 -L/opt/intel/compilers_and_libraries_2018/linux/lib/ia32 C++ benchmarks (except as noted below): icpc -m64 523.xalancbmk_r: icpc -m32 -L/opt/intel/compilers_and_libraries_2018/linux/lib/ia32 Fortran benchmarks: ifort -m64 Peak Portability Flags ---------------------- 500.perlbench_r: -DSPEC_LP64 -DSPEC_LINUX_X64 502.gcc_r: -D_FILE_OFFSET_BITS=64 505.mcf_r: -DSPEC_LP64 520.omnetpp_r: -DSPEC_LP64 523.xalancbmk_r: -D_FILE_OFFSET_BITS=64 -DSPEC_LINUX 525.x264_r: -DSPEC_LP64 531.deepsjeng_r: -DSPEC_LP64 541.leela_r: -DSPEC_LP64 548.exchange2_r: -DSPEC_LP64 557.xz_r: -DSPEC_LP64 Peak Optimization Flags ----------------------- C benchmarks: 500.perlbench_r: -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-mem-layout-trans=3 -fno-strict-overflow -L/home/cpu2017/je5.0.1-64/ -ljemalloc 502.gcc_r: -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/home/cpu2017/je5.0.1-32/ -ljemalloc 505.mcf_r: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/home/cpu2017/je5.0.1-64/ -ljemalloc 525.x264_r: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -fno-alias -L/home/cpu2017/je5.0.1-64/ -ljemalloc 557.xz_r: Same as 505.mcf_r C++ benchmarks: 520.omnetpp_r: -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/home/cpu2017/je5.0.1-64/ -ljemalloc 523.xalancbmk_r: -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/home/cpu2017/je5.0.1-32/ -ljemalloc 531.deepsjeng_r: Same as 520.omnetpp_r 541.leela_r: Same as 520.omnetpp_r Fortran benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -nostandard-realloc-lhs -align array32byte -L/home/cpu2017/je5.0.1-64/ -ljemalloc The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.2018-06-13.html http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.2018-06-13.xml http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.xml SPEC is a registered trademark of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. -------------------------------------------------------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact info@spec.org. Copyright 2017-2018 Standard Performance Evaluation Corporation Tested with SPEC CPU2017 v1.0.2 on 2018-11-09 06:21:21-0500. Report generated on 2018-11-27 13:40:45 by CPU2017 ASCII formatter v6067. Originally published on 2018-11-27.