SPEC(R) CINT2006 Summary Cisco Systems Cisco UCS B260 M4 (Intel Xeon E7-8890 v4, 2.20 GHz) Thu Dec 31 21:30:01 2009 CPU2006 License: 9019 Test date: May-2016 Test sponsor: Cisco Systems Hardware availability: Jul-2016 Tested by: Cisco Systems Software availability: Aug-2015 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 96 653 1440 S 400.perlbench 96 658 1420 S 400.perlbench 96 655 1430 * 401.bzip2 96 1077 860 S 401.bzip2 96 1077 860 S 401.bzip2 96 1077 860 * 403.gcc 96 636 1220 S 403.gcc 96 633 1220 * 403.gcc 96 632 1220 S 429.mcf 96 427 2050 S 429.mcf 96 427 2050 S 429.mcf 96 427 2050 * 445.gobmk 96 766 1310 S 445.gobmk 96 767 1310 * 445.gobmk 96 768 1310 S 456.hmmer 96 348 2570 S 456.hmmer 96 347 2580 S 456.hmmer 96 347 2580 * 458.sjeng 96 859 1350 S 458.sjeng 96 859 1350 S 458.sjeng 96 859 1350 * 462.libquantum 96 103 19300 S 462.libquantum 96 103 19300 * 462.libquantum 96 103 19300 S 464.h264ref 96 875 2430 S 464.h264ref 96 878 2420 * 464.h264ref 96 883 2410 S 471.omnetpp 96 830 723 * 471.omnetpp 96 830 723 S 471.omnetpp 96 831 722 S 473.astar 96 704 957 S 473.astar 96 704 957 * 473.astar 96 704 957 S 483.xalancbmk 96 374 1770 * 483.xalancbmk 96 375 1770 S 483.xalancbmk 96 373 1770 S ============================================================================== 400.perlbench 96 655 1430 * 401.bzip2 96 1077 860 * 403.gcc 96 633 1220 * 429.mcf 96 427 2050 * 445.gobmk 96 767 1310 * 456.hmmer 96 347 2580 * 458.sjeng 96 859 1350 * 462.libquantum 96 103 19300 * 464.h264ref 96 878 2420 * 471.omnetpp 96 830 723 * 473.astar 96 704 957 * 483.xalancbmk 96 374 1770 * SPECint(R)_rate_base2006 1750 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon E7-8890 v4 CPU Characteristics: Intel Turbo Boost Technology up to 3.40 GHz CPU MHz: 2200 FPU: Integrated CPU(s) enabled: 48 cores, 2 chips, 24 cores/chip, 2 threads/core CPU(s) orderable: 1,2 chips Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 256 KB I+D on chip per core L3 Cache: 60 MB I+D on chip per chip Other Cache: None Memory: 256 GB (16 x 16 GB 2Rx4 PC4-2400T-R, running at 1600 MHz) Disk Subsystem: 2 X 400 GB SAS SSD, RAID 0 Other Hardware: None SOFTWARE -------- Operating System: SUSE Linux Enterprise Server 12 SP1 (x86_64) 3.12.49-11-default Compiler: C/C++: Version 16.0.0.101 of Intel C++ Studio XE for Linux Auto Parallel: No File System: ext4 System State: Run level 3 (multi-user) Base Pointers: 32-bit Peak Pointers: 32/64-bit Other Software: Microquill SmartHeap V10.2 Submit Notes ------------ The config file option 'submit' was used. Platform Notes -------------- CPU performance set to Enterprise Power Technology set to Performance Energy Performance BIAS setting set to Balanced Performance Memory RAS configuration set to Maximum Performance Memory Power Saving Mode set to Disabled Sysinfo program /home/cpu2006-1.2/config/sysinfo.rev6914 $Rev: 6914 $ $Date:: 2014-06-25 #$ e3fbb8667b5a285932ceab81e28219e1 running on linux-xypl Thu Dec 31 18:30:02 2009 This section contains SUT (System Under Test) info as seen by some common utilities. To remove or add to this section, see: http://www.spec.org/cpu2006/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) CPU E7-8890 v4 @ 2.20GHz 2 "physical id"s (chips) 96 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 24 siblings : 48 physical 0: cores 0 1 2 3 4 5 8 9 10 11 12 13 16 17 18 19 20 21 24 25 26 27 28 29 physical 1: cores 0 1 2 3 4 5 8 9 10 11 12 13 16 17 18 19 20 21 24 25 26 27 28 29 cache size : 61440 KB From /proc/meminfo MemTotal: 264174296 kB HugePages_Total: 0 Hugepagesize: 2048 kB /usr/bin/lsb_release -d SUSE Linux Enterprise Server 12 SP1 From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 1 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12-SP1" VERSION_ID="12.1" PRETTY_NAME="SUSE Linux Enterprise Server 12 SP1" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12:sp1" uname -a: Linux linux-xypl 3.12.49-11-default #1 SMP Wed Nov 11 20:52:43 UTC 2015 (8d714a0) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Dec 31 16:37 SPEC is set to: /home/cpu2006-1.2 Filesystem Type Size Used Avail Use% Mounted on /dev/sda3 xfs 701G 19G 683G 3% /home Additional information from dmidecode: Warning: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Cisco Systems, Inc. EXM4.3.1.1.3.042620161123 04/26/2016 Memory: 16x 0xCE00 M393A2G40EB1-CRC 16 GB 2 rank 2400 MHz, configured at 1600 MHz 32x NO DIMM NO DIMM (End of data from sysinfo program) General Notes ------------- Environment variables set by runspec before the start of the run: LD_LIBRARY_PATH = "/home/cpu2006-1.2/libs/32:/home/cpu2006-1.2/libs/64:/home/cpu2006-1.2/sh" Binaries compiled on a system with 1x Intel Core i5-4670K CPU + 32GB memory using RedHat EL 7.1 Transparent Huge Pages enabled with: echo always > /sys/kernel/mm/transparent_hugepage/enabled Filesystem page cache cleared with: echo 1> /proc/sys/vm/drop_caches runspec command invoked through numactl i.e.: numactl --interleave=all runspec Base Compiler Invocation ------------------------ C benchmarks: icc -m32 -L/opt/intel/compilers_and_libraries_2016/linux/compiler/lib/ia32_lin C++ benchmarks: icpc -m32 -L/opt/intel/compilers_and_libraries_2016/linux/compiler/lib/ia32_lin Base Portability Flags ---------------------- 400.perlbench: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX_IA32 401.bzip2: -D_FILE_OFFSET_BITS=64 403.gcc: -D_FILE_OFFSET_BITS=64 429.mcf: -D_FILE_OFFSET_BITS=64 445.gobmk: -D_FILE_OFFSET_BITS=64 456.hmmer: -D_FILE_OFFSET_BITS=64 458.sjeng: -D_FILE_OFFSET_BITS=64 462.libquantum: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX 464.h264ref: -D_FILE_OFFSET_BITS=64 471.omnetpp: -D_FILE_OFFSET_BITS=64 473.astar: -D_FILE_OFFSET_BITS=64 483.xalancbmk: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -opt-prefetch -opt-mem-layout-trans=3 C++ benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -opt-prefetch -opt-mem-layout-trans=3 -Wl,-z,muldefs -L/sh -lsmartheap Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic16.0-official-linux64.html http://www.spec.org/cpu2006/flags/Cisco-Platform-Settings-V1.2-revE.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2006/flags/Intel-ic16.0-official-linux64.xml http://www.spec.org/cpu2006/flags/Cisco-Platform-Settings-V1.2-revE.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2016 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.2. Report generated on Thu Jun 30 13:53:20 2016 by CPU2006 ASCII formatter v6932. Originally published on 6 June 2016.