SPEC(R) CINT2006 Summary ScaleMP vSMP Foundation with PowerEdge M610 (Intel Xeon X5570, 2.93 GHz) Wed Aug 19 10:54:17 2009 CPU2006 License: 2929 Test date: Aug-2009 Test sponsor: ScaleMP Hardware availability: Apr-2009 Tested by: ScaleMP Software availability: Apr-2009 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 255 897 2780 S 400.perlbench 255 810 3070 * 400.perlbench 255 803 3100 S 401.bzip2 255 1198 2050 S 401.bzip2 255 1151 2140 S 401.bzip2 255 1158 2130 * 403.gcc 255 719 2850 S 403.gcc 255 714 2870 * 403.gcc 255 712 2880 S 429.mcf 255 636 3660 S 429.mcf 255 638 3640 S 429.mcf 255 637 3650 * 445.gobmk 255 805 3320 S 445.gobmk 255 780 3430 * 445.gobmk 255 780 3430 S 456.hmmer 255 917 2590 S 456.hmmer 255 908 2620 * 456.hmmer 255 908 2620 S 458.sjeng 255 956 3230 * 458.sjeng 255 956 3230 S 458.sjeng 255 956 3230 S 462.libquantum 255 662 7980 S 462.libquantum 255 652 8110 * 462.libquantum 255 649 8150 S 464.h264ref 255 1315 4290 S 464.h264ref 255 1303 4330 * 464.h264ref 255 1242 4540 S 471.omnetpp 255 754 2120 S 471.omnetpp 255 714 2230 S 471.omnetpp 255 748 2130 * 473.astar 255 939 1910 S 473.astar 255 920 1950 S 473.astar 255 931 1920 * 483.xalancbmk 255 618 2840 S 483.xalancbmk 255 535 3290 * 483.xalancbmk 255 513 3430 S ============================================================================== 400.perlbench 255 810 3070 * 401.bzip2 255 1158 2130 * 403.gcc 255 714 2870 * 429.mcf 255 637 3650 * 445.gobmk 255 780 3430 * 456.hmmer 255 908 2620 * 458.sjeng 255 956 3230 * 462.libquantum 255 652 8110 * 464.h264ref 255 1303 4330 * 471.omnetpp 255 748 2130 * 473.astar 255 931 1920 * 483.xalancbmk 255 535 3290 * SPECint(R)_rate_base2006 3150 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon X5570 CPU Characteristics: Intel Turbo Boost Technology is not-enabled CPU MHz: 2933 FPU: Integrated CPU(s) enabled: 128 cores, 32 chips, 4 cores/chip, 2 threads/core CPU(s) orderable: 8,16,24,32,40,48,56,64,96,128 chips Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 256 KB I+D on chip per core L3 Cache: 8 MB I+D on chip per chip Other Cache: 92 GB I+D off chip per system Memory: 768 GB (16 x 2 x 6 x 4 GB DDR3-1066R, ECC, CL9) Disk Subsystem: 16 x 160 GB SATA, 7200 RPM Other Hardware: None SOFTWARE -------- Operating System: Red Hat Enterprise Linux Server release 5.3 (Tikanga) Kernel: 2.6.21.7-16.vSMP.nomc Compiler: Intel C++ Compiler 11.0 for Linux Build 20081105 Package ID: l_cproc_p_11.0.074 Auto Parallel: No File System: xfs System State: Multi-user, run level 3 Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: Hoard (libhoard) 3.7.1, released Feb. 08, 2008 ScaleMP vSMP Foundation 2.0.65.35 Submit Notes ------------ The config file option 'submit' was used. numactl was used to bind copies to the cores Platform Notes -------------- ScaleMP vSMP Foundation: 2.0.65.35 Other Cache: ScaleMP vSMP Foundation manages cache coherency between the InfiniBand-connected systems via multiple concurrent memory coherency mechanisms, on a per-block basis, based on real-time memory activity access patterns. This mechanism reserves 92 GB of the main memory across all boards (distributed), which is used as a 4th level cache. Hardware Details: System was aggregated using 16 X Dell PowerEdge M610. The servers were connected with Melanox InfiniBand QDR and a QDR switch. CPU Characteristics: Intel Turbo Boost Technology not-enabled: As the prerequisites listed below for enablement of this technology did not exist. The prerequisites for Turbo Boost Technology are: - Hardware: Enabling Turbo Boost Technology require BIOS setting. - Software: OS needs to be ACPI-aware and set P0 power state. Base Compiler Invocation ------------------------ C benchmarks: icc C++ benchmarks: icpc Base Portability Flags ---------------------- 400.perlbench: -DSPEC_CPU_LINUX_IA32 462.libquantum: -DSPEC_CPU_LINUX 483.xalancbmk: -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -xSSE4.2 -ipo -O3 -no-prec-div -static -inline-calloc -opt-malloc-options=3 -opt-prefetch C++ benchmarks: -xSSE4.2 -ipo -O3 -no-prec-div -opt-prefetch -Wl,-z,muldefs /mnt/test/SPEC2006/cpu2006/libhoard.so Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags file that was used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic11.0-int-linux64-revE.20090918.html You can also download the XML flags source by saving the following link: http://www.spec.org/cpu2006/flags/Intel-ic11.0-int-linux64-revE.20090918.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2014 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.1. Report generated on Wed Jul 23 03:39:40 2014 by CPU2006 ASCII formatter v6932. Originally published on 18 September 2009.