SPEC(R) CINT2006 Summary IBM Corporation IBM System x3800 Wed Dec 6 02:06:09 2006 CPU2006 License: 11 Test date: Dec-2006 Test sponsor: IBM Corporation Hardware availability: Oct-2006 Tested by: IBM Corporation Software availability: Aug-2006 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 16 1765 88.6 S 400.perlbench 16 1760 88.8 S 400.perlbench 16 1762 88.7 * 401.bzip2 16 2134 72.4 * 401.bzip2 16 2127 72.6 S 401.bzip2 16 2135 72.3 S 403.gcc 16 5782 22.3 * 403.gcc 16 5765 22.3 S 403.gcc 16 5793 22.2 S 429.mcf 16 2663 54.8 * 429.mcf 16 2659 54.9 S 429.mcf 16 2669 54.7 S 445.gobmk 16 2062 81.4 S 445.gobmk 16 2063 81.4 S 445.gobmk 16 2062 81.4 * 456.hmmer 16 2434 61.3 * 456.hmmer 16 2438 61.2 S 456.hmmer 16 2433 61.4 S 458.sjeng 16 3105 62.4 * 458.sjeng 16 3106 62.3 S 458.sjeng 16 3017 64.2 S 462.libquantum 16 13485 24.6 S 462.libquantum 16 13478 24.6 S 462.libquantum 16 13480 24.6 * 464.h264ref 16 2303 154 * 464.h264ref 16 2303 154 S 464.h264ref 16 2298 154 S 471.omnetpp 16 3239 30.9 S 471.omnetpp 16 3245 30.8 S 471.omnetpp 16 3243 30.8 * 473.astar 16 1846 60.8 * 473.astar 16 1842 61.0 S 473.astar 16 1847 60.8 S 483.xalancbmk 16 1404 78.6 S 483.xalancbmk 16 1406 78.5 S 483.xalancbmk 16 1405 78.6 * ============================================================================== 400.perlbench 16 1762 88.7 * 401.bzip2 16 2134 72.4 * 403.gcc 16 5782 22.3 * 429.mcf 16 2663 54.8 * 445.gobmk 16 2062 81.4 * 456.hmmer 16 2434 61.3 * 458.sjeng 16 3105 62.4 * 462.libquantum 16 13480 24.6 * 464.h264ref 16 2303 154 * 471.omnetpp 16 3243 30.8 * 473.astar 16 1846 60.8 * 483.xalancbmk 16 1405 78.6 * SPECint(R)_rate_base2006 57.7 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon 7130N CPU Characteristics: 667 MHz bus CPU MHz: 3133 FPU: Integrated CPU(s) enabled: 8 cores, 4 chips, 2 cores/chip, 2 threads/core CPU(s) orderable: 1,2,4 chips Primary Cache: 12 K micro-ops I + 16 KB D on chip per core Secondary Cache: 1 MB I+D on chip per core L3 Cache: 8 MB I+D on chip per chip Other Cache: None Memory: 32 GB (16 x 2048 MB ECC PC2-3200) Disk Subsystem: 73 GB SAS, 10k RPM Other Hardware: None SOFTWARE -------- Operating System: Microsoft Windows Server 2003 Enterprise x64 Edition + SP1 (64-bit) Compiler: Intel C++ Compiler for IA32 version 9.1 Build no 20060816 Microsoft Visual Studio .Net 2003 (for libraries) Auto Parallel: No File System: NTFS System State: Default Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: Smart Heap Library, Version 8 General Notes ------------- Bios Settings Hardware Prefetch enabled Memory Array set to High-Performance Memory Array Base Compiler Invocation ------------------------ C benchmarks: icl -Qvc7.1 -Qc99 C++ benchmarks: icl -Qvc7.1 Base Portability Flags ---------------------- 403.gcc: -DSPEC_CPU_WIN32 464.h264ref: -DSPEC_CPU_NO_INTTYPES -DWIN32 Base Optimization Flags ----------------------- C benchmarks: -fast /F512000000 shlw32m.lib -link /FORCE:MULTIPLE C++ benchmarks: -fast -Qcxx_features /F512000000 shlw32m.lib -link /FORCE:MULTIPLE Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags file that was used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.05.html You can also download the XML flags source by saving the following link: http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.05.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2014 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.0. Report generated on Tue Jul 22 10:09:53 2014 by CPU2006 ASCII formatter v6932. Originally published on 26 December 2006.