SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer p5 570 (1900 MHz, 16 CPU)
SPECint_rate2000 = 294    
SPECint_rate_base2000 = 273    
SPEC license # 11 Tested by: IBM Test date: Jun-2004 Hardware Avail: Sep-2004 Software Avail: Aug-2004
Graph Scale Benchmark Base
Copies		 Base
Runtime		 Base
Ratio		 Copies Runtime Ratio
164.gzip base result bar (220)
164.gzip peak result bar (220)		 164.gzip 32 237    220     32 237    220    
175.vpr base result bar (233)
175.vpr peak result bar (233)		 175.vpr 32 223    233     32 223    233    
176.gcc base result bar (324)
176.gcc peak result bar (324)		 176.gcc 32 126    324     32 126    324    
181.mcf base result bar (324)
181.mcf peak result bar (318)		 181.mcf 32 206    324     32 210    318    
186.crafty base result bar (220)
186.crafty peak result bar (300)		 186.crafty 32 169    220     32 124    300    
197.parser base result bar (172)
197.parser peak result bar (263)		 197.parser 32 389    172     32 254    263    
252.eon base result bar (352)
252.eon peak result bar (352)		 252.eon 32 137    352     32 137    352    
253.perlbmk base result bar (224)
253.perlbmk peak result bar (247)		 253.perlbmk 32 298    224     32 271    247    
254.gap base result bar (273)
254.gap peak result bar (286)		 254.gap 32 149    273     32 143    286    
255.vortex base result bar (441)
255.vortex peak result bar (464)		 255.vortex 32 160    441     32 152    464    
256.bzip2 base result bar (313)
256.bzip2 peak result bar (317)		 256.bzip2 32 178    313     32 176    317    
300.twolf base result bar (281)
300.twolf peak result bar (279)		 300.twolf 32 397    281     32 400    279    
  SPECint_rate_base2000 273      
  SPECint_rate2000 294    

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM eServer p5 570 (1900 MHz, 16 CPU)
CPU: POWER5
CPU MHz: 1900
FPU: Integrated
CPU(s) enabled: 16 cores, 8 chips, 2 cores/chip (SMT on)
CPU(s) orderable: 2,4,8,12,16
Parallel: No
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified (on chip)/chip
L3 Cache: 36MB unified (off chip)/DCM, 8 DCM/SUT
Other Cache: none
Memory: 64x1 GB DDR2
Disk Subsystem: 1x36GB SCSI, 15K RPM
Other Hardware:
Software
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 7.0 for AIX
File System: AIX/JFS2
System State: Multi-User
Notes / Tuning Information 
 Portability Flags:
   176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
   186.crafty:   -DAIX
   252.eon:      srcalt=fmax_errno 
                 -I. -DNDEBUG
   253.perlbmk:  -DSPEC_CPU2000_AIX
   254.gap:      -DSYS_IS_BSD -DSYS_STRING_H -DSYS_HAS_TIME_PROTO
                 -DSYS_HAS_MALLOC_PROTO -DSYS_HAS_CALLOC_PROTO
   300.twolf:    -DHAVE_SIGNED_CHAR
 
 
 Base Optimization Flags:
   C:    -qpdf1/pdf2 
         -O5 -blpdata -qalign=natural
   C++:  -qpdf1/pdf2 
         -O5 -lhmu -qalign=natural
 
 
 Peak Optimization Flags
   164.gzip:     -qpdf1/pdf2
                 -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -D_ILS_MACROS
                 "CC=xlc"
   175.vpr:      basepeak = 1 
   176.gcc:      basepeak = 1
   181.mcf:      fdpr -quiet -R3
                 -O5 -blpdata -qfdpr
   186.crafty:   -qpdf1/pdf2
                 fdpr -quiet -R3
                 -O4 -q64 -qfdpr -qarch=pwr3 -qtune=pwr3 -D_ILS_MACROS
   197.parser:   -qpdf1/pdf2
                 fdpr -quiet -R3
                 -O4 -blpdata -D_ILS_MACROS -qfdpr -qarch=pwr3 -qtune=pwr3
   252.eon:      basepeak = 1
   253.perlbmk:  -qpdf1/pdf2
                 -O5 -D_ILS_MACROS -lhmu -qalign=natural
   254.gap:      -qpdf1/pdf2
                 -O4 -qarch=pwr4 -qtune=pwr4 -D_ILS_MACROS -lhmu -qalign=natural
   255.vortex:   -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural -D_ILS_MACROS -blpdata
   256.bzip2:    -qpdf1/pdf2
                 -O5 -blpdata -qarch=pwr3 -qtune=pwr3 -qalign=natural
   300.twolf:    -O5 -lhmu -blpdata -qalign=natural
                 "CC = xlc"

 Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
 was used with 252.eon for POSIX-compatibility.

 SMT: Acronym for "Simultaneous Multi-Threading". A processor technology that allows
      the simultaneous execution of multiple thread contexts within a single processor
      core. (Enabled by default)
 DCM: Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
 SUT: Acronym for "System Under Test"

 ulimits set to unlimited.
 Large page mode and memory affinity were set as follows:
    vmo -r -o lgpg_regions=400 -o lgpg_size=16777216 -o memory_affinity=1
    chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
    reboot -q
    export MEMORY_AFFINITY=MCM

For questions about this result, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 28-Jul-2004

Generated on Wed Jul 28 12:26:14 2004 by SPEC CPU2000 HTML formatter v1.01